This application claims priority to Korean Patent Application No. 2003-0094264, filed on Dec. 20, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to input buffers, more particularly, to an input buffer generating an output signal of a predetermined signal type regardless of the signal type of at least one input signal.
2. Description of the Related Art
FIG. 1 shows a system 100 including a conventional multi-port/multi-media semiconductor device 150 and a circuit block 110. The circuit block 110 includes a plurality of application circuits such as an audio input circuit 111, a video input circuit 115, a digital media processing circuit 119, an audio output circuit 127, and a video output circuit 131. Such circuits 111, 115, 119, 127, and 121 may be implemented as separate semiconductor chips.
The audio input circuit 111, the video input circuit 115, the digital media processing circuit 119, the audio output circuit 127, the video output circuit 131, and the multi-port/multi-media semiconductor device 150 each use unique signal levels to exchange data with external devices. A signal level characterizes a signal type defined by a direct current (DC) reference level and a swing width about the DC reference level (hereinafter referred to as “a reference level and a swing width”).
Examples of conventional signal types include a transistor-transistor logic (TTL) level, a complementary metal oxide semiconductor device (CMOS) level, a stub series transceiver logic (SSTL) level, a Rambus signal logic (RSL) level, and a differential Rambus signaling (DRSL) level. As interfacing speed increases, the swing width is reduced.
To input and output data at high speed, the audio input circuit 111, the video input circuit 115, the digital media processing circuit 119, the audio output circuit 127, the video output circuit 131, and the multi-port/multi-media semiconductor device 150 include input/output (I/O) interfaces 113, 117, 121, 123, and 125, respectively. Each of the I/O interfaces 113, 117, 121, 123, and 125 converts a signal level of an input signal to a signal level processed by the corresponding application circuit. Each of the I/O interfaces 113, 117, 121, 123, and 125 may be implemented as separate chips.
For example, assume that a signal level (or a signal system) of a signal output from the video input circuit 115 (processing a video signal Vin) is different from that used in the semiconductor device 150. In that case, the I/O interface 117 which is a transmitting circuit of the video input circuit 115 converts the signal level and the amplitude of the signal from the video input circuit. The converted signal is transmitted to the semiconductor device 150 via a channel. Then, an input buffer 151 of the semiconductor device 150 converts the signal level and amplitude of the signal input via the channel into those processed by the semiconductor device 150.
Similarly, the I/O interface 113 of the audio input circuit 111 (processing an audio signal Ain) converts the level and the amplitude of a signal from the audio input circuit 111. The I/O interface 113 of the audio input circuit 111 transmits such a converted signal to the input buffer 151 of the semiconductor device 150.
The digital media processing circuit 119 exchanges signals with the semiconductor device 150 via the I/O interfaces 121, 123, and 125, which are transmitting/receiving circuits. Each of the I/O interfaces 121, 123, and 125 converts the level and the amplitude of input and output signals.
The audio output circuit 127 and the video output circuit 131 process signals from an output buffer 157 of the semiconductor device 150. The audio output circuit 127 and the video output circuit 131 also output an audio output signal Aout and a video output signal Vout, respectively.
In this manner in the prior art, the application circuits 111, 115, 119, 127, and 131 and the semiconductor device 150 using different signal levels require additional chips, 113, 117, 121, 123, 125, 151, 153, 155, and 157 for interfacing with each-other to exchange signals at high speed. As the number of application circuits exchanging signals with the multi-port/multi-media semiconductor device 150 increases, the number of interfacing chips converting different signal levels also increases, resulting in an increase in the cost of the entire system.
Thus, a mechanism is desired for decreasing the number of interfacing chips during signal exchange between application circuits and the semiconductor device 150.